Typically, semi-conductor chips have been connected to electrical circuit features including pads and lines (traces) on mounting substrates by wire bonding, tape-automated bonding, and flip-chip bonding. In wire bonding, the chip is positioned on a substrate with a bottom or back surface (not including contacts thereon) of the chip abutting the substrate and with the contact-bearing top surface facing upwardly. Individual wires (gold or aluminum) are connected between the chip's contacts and respective substrate pads. In tape automated bonding, a flexible dielectric tape with a prefabricated array of leads thereon is positioned over the chip and substrate and the individual leads are bonded to the chip's contacts and substrate pads. A common problem with both wire bonding and conventional tape automated bonding is that the substrate pads are oriented externally of the substrate area covered by the positioned chip. This requires the entire assembly to be substantially larger than it otherwise would be. Because the speed with which a microelectronic assembly operates is inversely related to its size, this much larger structure presents a relatively serious drawback, especially when considering the high-density (and high-speed) microelectronic package structures mandated today.
To overcome these limitations, flip-chip mounting has been developed. In this methodology, the actual contact-bearing surface of the chip is placed face down on the substrate's upper surface. Each chip contact is joined by a solder bond, e.g., formed from a solder ball, to a corresponding contact pad on the substrate. That is, this method involves positioning several solder balls on the substrate or chip, juxtaposing the chip with the contact substrate in the front-face-down orientation over the substrate's contact surface, and melting (reflowing) the solder. In some situations, this melting or reflow process is referred to as controlled collapse chip connection (C4). Most significantly, this flip-chip process yields a very compact assembly, which occupies an area of the substrate no larger than the area of the chip itself. This area, understandably, is less than that of the area required for assemblies formed by the aforementioned wire-bonding and tape automated bonding, thereby resulting in advantages in area and speed for the resulting package.
There are, however, at least two potential problems associated with flip-chip technology. One involves the requirement to use an under-fill material (also referred to in the industry as encapsulating material) to surround the formed solder connections and thereby protect same during assembly operation. The use of such material adds to the overall cost of the final package, but also presents problems with respect to rework and repair of the package structure should it become inoperative for any reason. The encapsulating material is hardened at such a time. Its removal is both difficult from a manufacturing standpoint, but also potentially damaging to the protected connections.
A second and perhaps most important potential problem with flip-chip methodology is the formation of thermal stresses in the area of the formed connections. The solder bonds between the chip and substrate contacts are substantially rigid. Changes in the size of the chip and of the substrate due to thermal expansion and contraction during package operation create substantial stresses in these rigid bonds, which in turn can lead to bond fatigue failure. That is, these contact-to-contact connections, also referred to in the art as input/output (I/O) connections, are normally subject to substantial stresses due to thermal cycling within the package during package operation. For example, electrical power dissipated during operation tends to heat up both the substrate and associated chip or chips, and, when the operation is terminated, both the chip(s) and substrate cool. Because the substrate and the chip(s) are constructed of significantly different materials, which in turn have different coefficients of thermal expansion (CTEs), the chip(s) and substrate expand and contract by different amounts and, significantly, at different rates. This motion of the chip(s) relative to the substrate may cause movement of the I/O connections, placing these under mechanical stress. Repeated occurrence of these stresses may in turn cause breakage of the I/O connections and corresponding ultimate failure of the chip(s) and thus the entire package. When forming packages utilizing an organic chip carrier (where the substrate is of organic material, much desired in many of today's products), there are even greater differences in the CTEs than in previous packages where ceramic or similar material was used for the substrate members. Consideration must also be given to the different CTE of the solder material used to form the bonds between each respective mating contact pair.
One attempt to overcome the foregoing flip-chip problem has involved the use of separate interposers or the like structures between the chip(s) and accommodating substrates. Such structures usually have a plurality of terminals disposed on a flexible, sheet-like layer of dielectric, e.g., polymer material. In one example of the use of such an interconnecting structure, the interposer may be disposed on the front or contact-bearing surface of the chip with the interposer's terminals facing upwardly, away from the chip. The terminals are then connected to the contacts of the chip. This connection may be accomplished by bonding prefabricated leads on the interposer to the chip contacts, using a specific tool designed for this purpose. The completed chip-interposer assembly is then connected to a substrate, e.g., a printed circuit board or a chip carrier, by bonding the contacts of the interposer to the desired, corresponding contacts of the substrate. Because the leads and the dielectric layer of the interposer are flexible, the terminals on the interposer may move relative to the contacts on the chip without imposing significant stresses on the bonds between the leads and the chip, or on the bonds between the contacts and the substrate. This resulting assembly may thus compensate for thermal effects. Moreover, if the interposer includes a compliant (e.g., elastomeric) layer, this compliant structure permits displacement of the individual interposer contacts in an independent manner relative to the chip.
The following patents describe various chip connection structures, including those involving the use of interposers and the like. As seen, some of these involve the formation of compressible (also referred to as compliant or flexible) contact structures on the chip. The listing of these patents is not to be construed that any are prior art to the presently claimed invention. Nor is the listing thereof an acknowledgement that an exhaustive search of the prior art has been completed.
In U.S. Pat. No. 4,845,542, issued to Bezuk, et al. for “Interconnect For Layered Integrated Circuit Assembly” there are described electrical and/or mechanical interconnections between adjacent wafers (chips) within integrated circuit assemblies and structural integrity of those interconnections under temperature cycling conditions. Laser-assisted chemical vapor deposition is utilized to fabricate precisely configured metal posts, which serve as such interconnections.
In U.S. Pat. No. 5,148,265, issued to Khandros, et al. for “Semiconductor Chip Assemblies With Fan-In Leads” there is described a semi-conductor chip having contacts on the periphery of its top surface with an interposer overlying the central portion of the top surface. Peripheral contact leads extend inwardly from the peripheral contacts to central terminals on the interposer. The terminals on the interposer may be connected to a substrate using techniques commonly employed in surface mounting of electrical devices, such as solder bonding. The leads, and preferably the interposer, are described as being flexible so that the terminals are movable with respect to the contacts on the chip, to compensate for differential thermal expansion of the chip and substrate. The interposer may be provided with a compliant layer disposed between the terminals and the chip to permit slight vertical movement of the terminals towards the chip during testing operations.
In U.S. Pat. No. 5,148,266, issued to Khandros, et al. for “Semiconductor Chip Assemblies Having Interposer And Flexible Head” there is described a semi-conductor chip assembly which is mounted to contact pads in a compact area array, in which an interposer is disposed between the chip and the substrate. The contacts on the chip are connected to terminals on the interposer by flexible leads extending through apertures in the interposer. The terminals on the interposer in turn are bonded to the contact pads on the substrate. Flexibility of the leads permits relative movement of the contacts on the chip relative to the terminals and the contact pads of the substrate and hence relieves the stresses caused by differential thermal expansion.
In U.S. Pat. No. 5,455,390, issued to Distefano, et al. for “Microelectronics Unit Mounting With Multiple Lead Bonding” there is described the use of a flexible, dielectric top sheet having top and bottom surfaces with a plurality of terminals mounted on the top sheet. A support layer is disposed underneath the top sheet, this support layer having a bottom surface remote from the top sheet. A plurality of electrically conductive, elongated leads are connected to the terminals on the top sheet and extend generally side by side downwardly from the terminals through the support layer. Each lead has a lower end at the bottom surface of the support layer. The lower ends of the leads have conductive bonding materials as, for example, eutectic bonding metals. The support layer surrounds and supports the leads.
In U.S. Pat. No. 5,863,814, issued to Alcoe, et al. for “Electronic Package With Compressible Heatsink Structure” there is described an electronic package wherein a semi-conductor chip on a circuitized substrate is thermally coupled to a heat sink in a separable manner using a plurality of compressible, thermally conductive members (e.g., solder balls). These members are compressed and permanently deformed as part of the thermal coupling.
In U.S. Pat. No. 6,086,808, issued to Sørensen, et al. for “Repositioning Of Articles Between Different Positions Within An Intermittently Accessible Space” there is described the formation of pads (contacts) which are attached to a high density printed circuit board having a plurality of thru-holes opening on the top surface. A plurality of these pads are formed on a carrier sheet so that each of the pads have a copper layer proximate to the carrier sheet and a joining metal layer formed on top of said copper layer. The plurality of pads are positioned on the carrier sheet so that these are aligned with the thru-hole pattern on the top surface of the PCB, the pads being laminated to the thru-holes on the top surface using the joining metal, and the carrier sheet being separated from the plurality of pads that are joined to the thru-holes so that the copper layer is exposed. The pads may possess a variety of shapes such as disk-shaped, elongated, or rectangular, and can cover one or multiple thru-holes. An electrical component may be soldered to the pad. The pad and thru-hole may be compressed so that the top surface of the pad is even or flush with the top surface of an external dielectric surface.
In U.S. Pat. No. 6,104,087, issued to Distefano, et al. for “Microelectronic Assemblies with Multiple Leads” there is described a micro-electronic connection component which includes a dielectric sheet having an area array of elongated, strip-like leads. Each lead has a terminal end fastened to the sheet and a tip end detachable from the sheet. Each lead extends horizontally parallel to the sheet, from its terminal end to its tip end. The tip ends are attached to a second element, such as another dielectric sheet or a semi-conductor wafer (chip). The first and second elements are then moved relative to one another to advance the tip end of each lead vertically away from the dielectric sheet and deform the leads into a bent, vertically extensive configuration. The preferred structures provide semi-conductor chip assemblies with a planar area array of contacts on the chip, an array of terminals on the sheet positioned so that each terminal is substantially over the corresponding contact, and an array of metal S-shaped ribbons connected between the terminals and contacts. A compliant dielectric material may be provided between the sheet and chip, substantially surrounding the S-shaped ribbons.
In U.S. Pat. No. 6,150,255, issued to Downes, Jr., et al. for “Method of Planarizing A Curved Substrate and Resulting Structure” there is described a method for providing a planarized substrate with dendritic connections of solder balls, especially a multilayer ceramic substrate is provided. In the case where the substrate has a raised central portion on the top surface, on which are disposed top surface metallurgy pads, a layer of conformable photoimagable material is placed over the top surface. The photoimagable material is exposed and developed in a pattern corresponding to the pattern of the top surface metallurgy pads to form via holes in the photoimagable material. Copper is plated in the vias in contact with the top surface metallurgy pads. The exposed surface of the photoimagable surface is then planarized, preferably by mechanical polishing to form a flat planar surface, with the ends of the vias exposed. Dendritic connector pads are then grown on the exposed ends of the vias to which solder ball connections of a chip are releasably connected.
In U.S. Pat. No. 6,187,615, issued to Kim, et al. for “Chip Scale Packages And Methods For Manufacturing The Chip Scale Packages At Wafer Level” there is described a chip scale package (CSP) manufactured at wafer-level and including a chip, a conductor layer for redistribution of the chip pads of the chip, one or two insulation layers and multiple bumps, which are interconnected to respective chip pads by the conductor layer and are the terminals of the CSP. In addition, in order to improve the reliability of the CSP, a reinforcing layer, an edge protection layer and a chip protection layer are provided. The reinforcing layer absorbs stress applied to the bumps when the CSP are mounted on a circuit board and used for an extended period, and extends the life of the bumps.
In U.S. Pat. No. 6,211,572, issued to Fjelstad, et al. for “Semiconductor Chip Package With Fan-In Leads” there is described a compliant semi-conductor chip package with fan-in leads and a method for manufacturing same. The package contains a multiplicity of bond ribbons connected between the contacts of a semi-conductor chip and corresponding terminals on a top surface of a compliant layer. The compliant layer provides stress relief to the bond ribbons encountered during handling or affixing the assembly to an external substrate. The chip package also contains a dielectric layer, adjacent ends of the bond ribbons. The dielectric layer relieves mechanical stresses associated with the thermal mismatch of assembly and substrate materials during thermal cycling. The assembly can be manufactured without the need for any bond wiring tools since the bond ribbons are patterned and formed during a standard photolithographic stage within the manufacturing process.
In U.S. Pat. No. 6,281,111, issued to Ohsumi for “Semiconductor Apparatus and Method For Fabricating The Same” there is described a semi-conductor integrated circuit including a conductive pattern, an insulating layer formed on the semi-conductor integrated circuit to form a plurality of base members having uneven heights, an opening formed through the insulating layer to expose a part of the conductive pattern and a conductive layer formed on the insulating layer and the opening.
In U.S. Pat. No. 6,372,527, issued to Khandros, et al. for “Methods of Making Semiconductor Chip Assemblies” there is described a method of making semi-conductor chip assemblies which includes providing a semi-conductor wafer including a plurality of semi-conductor chips having contacts on a contact bearing surface thereof and providing a substrate having a first surface with a plurality of conductive terminals located thereon and a second surface. The substrate is then assembled with the wafer so that the terminals are electrically connected to the contacts on the chips and portions of the substrate are removed to expose the terminals. In certain embodiments, an encapsulating material may be injected between the wafer and the substrate for providing a compliant layer.
In U.S. Pat. No. 6,521,970, issued to Takiar, et al. for “Chip Scale Package With Compliant Leads” there is described an integrated circuit structure having an air gap formed between the integrated circuit die of the structure and compliant leads located over and conductively attached to the die. Contact bumps offset on the compliant leads provide for connection of the integrated circuit structure to other substrates. In some embodiments, the compliant leads include a conductive layer overlaid with an outer resilient layer, and may further include an inner resilient layer beneath the conductive layer. The outer resilient layer has a via (hole) formed through it exposing the underlying conductive layer. This via hole is offset along the compliant lead a horizontal distance from the bond pad to which the compliant lead is conductively coupled. The chip scale structure provides a compliant connection between the die and any substrate to which the die is attached.
In U.S. Pat. No. 6,528,349, issued to Patel, et al. for Monolithically-Fabricated Compliant Wafer-Level Package With Wafer Level Reliability And Functionality Testability” there is described a monolithically fabricated compliant wafer level package having a compliant layer and a compliant interconnect passing therein, the compliant interconnects being provided so that electrical and mechanical connections may be supported across the compliant layer. These are also constructed so that stresses resulting from motion of various electrical components are accommodated. In the described method of providing a substrate having such a compliant layer, the compliant layer includes a via hole that exposes a die pad on the substrate.
In U.S. Pat. No. 6,642,083, issued to Miyazaki, et al. for “Semiconductor Device and Manufacturing Method Thereof” there is described a Ball Grid Array (BGA) type semi-conductor package which includes a semi-conductor chip formed with bonding pads, an elastomer bonded to the semi-conductor chip, a flexible wiring substrate bonded to the elastomer and formed with wirings connected at one end of the bonding pads of the semi-conductor chip, a solder resist formed on the main surface of the flexible wiring substrate and solder bump electrodes connected to the other ends of the wirings. The solder bump electrodes are connected with the wirings by way of through holes formed in the resist.
In U.S. Pat. No. 7,292,055, issued to Egitto, et al. for “Interposer For Use With Test Apparatus” there is described an interposer in which at least two dielectric layers bonded to each other sandwich a plurality of conductors therebetween. The conductors each electrically couple a respective pair of opposed electrical contacts, which protrude from openings within the dielectric layers. The resulting interposer is ideally suited for use as part of a test apparatus to interconnect highly dense patterns of solder ball contacts of a semi-conductor chip to lesser dense arrays of contacts on the apparatus's printed circuit board.
In U.S. Pat. No. 7,455,915, issued to Johnson for Selective Application Of Conductive Material To Substrates By Pick And Place of Compliant Contact Arrays” there is described the application of a conductive material with a compliant under layer onto selected pads of a substrate, includes forming at least one “padstack” by patterning a sheet including a stack of material layers. These padstacks may include a first conductive top layer, one or more underlying layers, and a bottom attachment layer, such as a solder layer. At least one flexible, or compliant, layer is disposed in the sheet between the top and attachment layers. The compliant layer may be a conductive elastomer. The top layer of the padstacks are adhered to a soluble tape, and this composite structure is moved into place over the circuit board by means of a pick and place operation. The placement of the padstacks is followed by a solder reflow to adhere the padstacks to the contact pads of the substrate, and by a wash cycle with a solvent to remove the soluble tape.
In U.S. Pat. No. 7,456,046, issued to Buchwalter, et al. for “Method To Create Flexible Connections For Integrated Circuits” there is described a method of producing flexible interconnections for integrated circuits, and, in particular, the forming of flexible or compliant interconnections preferably by a laser-assisted chemical vapor deposition process in semi-conductor or glass substrate-based carriers which are employed for mounting and packaging multiple integrated circuit chips.
In U.S. Pat. No. 7,511,518, issued to Egitto, et al. for Method Of Making An Interposer” there is described a method of making an interposer in which at least two dielectric layers are bonded to each other to sandwich a plurality of conductors therebetween. The conductors each electrically couple a respective pair of opposed electrical contacts, which are formed within and protrude from openings, which are also formed within the dielectric layers as part of this method. The resulting interposer is ideally suited for use as part of a test apparatus to interconnect highly dense patterns of solder ball contacts of a semi-conductor chip to lesser dense arrays of contacts on the apparatus' printed circuit board.
In U.S. Pat. No. 7,534,652, issued to Haba, et al. for Microelectronic Elements With Compliant Terminal Mountings And Methods For Making The Same” there is described a dielectric structure formed by molding so that a first surface is shaped by contact with the mold. The opposite second surface is applied to the front surface of a wafer element. The dielectric layer may include protruding bumps and terminals may be formed on the bumps. The bumps may be of a precise height. The terminals lie at a precisely controlled height above the front surface of the wafer element and may include projecting posts, which extend above a surrounding solder mask layer.
As defined below, the present invention comprises the formation of a compliant-type contact structure on a semiconductor chip surface which is able, in turn, form effective electrical connections to a hosting substrate such as a PCB or chip carrier, with or without using solder bonds. The resulting formed connections do not require the use of under-fill or encapsulating materials, but such materials may be used if desired. Absent use of such under-fill material, however, the formed interconnections as defined herein enable rework and repair of the formed final package structure, thereby significantly reducing costs incurred if such a complete package were found to be inoperative to the extent that full replacement was deemed necessary.
It is believed that such an invention will represent a significant advancement in the art.